april 2013 april 2013 april 2013 april 2013 april 2013 dsc-3514/11 1 ?2013 integrated device technology, inc. features 128k x 8 advanced high-speed cmos static ram jedec revolutionary pinout (center power/gnd) for reduced noise. equal access and cycle times ? commercial: 12/15/20ns ? industrial: 15/20ns one chip select plus one output enable pin bidirectional inputs and outputs directly ttl-compatible low power consumption via chip deselect available in a 32-pin 400 mil plastic soj. functional block diagram description the IDT71124 is a 1,048,576-bit high-speed static ram organized as 128k x 8. it is fabricated using high-performance, high-reliability cmos technology. this state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. the jedec centerpower/gnd pinout reduces noise generation and improves system performance. the IDT71124 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns available. all bidirectional inputs and outputs of the IDT71124 are ttl-compatible and operation is from a single 5v supply. fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. the IDT71124 is packaged in a 32-pin 400 mil plastic soj. address decoder 1,048,576-bit memory array i/o control ? a 0 a 16 3514 drw 01 8 8 i/o 0 - i/o 7 8 control logic we oe cs , cmos static ram 1 meg (128k x 8-bit) revolutionary pinout IDT71124
6.42 2 IDT71124 cmos static ram 1 meg (128k x 8-bit) revolutionary pinout commercial and industrial temperatur e ranges capacitance (t a = +25c, f = 1.0mhz) symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 8 pf c i/o i/o capacitance v out = 3dv 8 pf 3514 tbl 03 recommended dc operating conditions note: 1. this parameter is guaranteed by device characterization, but is not production tested. symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ___ _ v cc +0.5 v v il input low voltage -0.5 (1 ) ___ _ 0.8 v 3514 tbl 05 grade temperature gnd v cc commercial 0c to +70c 0v 5.0v 10% industrial ?40c to +85c 0v 5.0v 10% 3514 tbl 04 recommended operating temperature and supply voltage pin configuration notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. v term must not exceed vcc + 0.5v. truth table (1,2) soj top view 5 6 7 8 9 10 11 12 a 0 a 1 a 2 1 2 3 4 32 31 30 29 28 27 26 25 24 23 22 21 a 15 a 3 cs i/o 1 v cc a 14 oe i/o 7 i/o 6 gnd i/o 5 3514 drw 02 gnd 13 20 14 19 15 18 16 a 7 17 i/o 2 i/o 3 we a 4 a 5 a 6 a 12 a 11 a 10 a 9 a 8 so32-3 i/o 0 a 16 a 13 v cc i/o 4 , notes: 1. h = v ih , l = v il , x = don't care. 2. vlc = 0.2v, vhc = vcc -0.2v. 3. other inputs vhc or vlc. cs oe we i/o function llhdata out read data lx ldata in write data l h h high-z output disabled h x x high-z deselected - standby (i sb ) v hc (3) x x high-z deselected - standby (i sb1 ) 3514 tbl 01 absolute maximum ratings (1) symbol rating value unit v term (2 ) terminal voltage with respect to gnd -0.5 to +7.0 (2) v t a operating temperature 0 to +70 o c t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 1.25 w i out dc output current 50 ma 3514 tbl 02
6.42 idt 71124 cmos static ram 1 meg (128k x 8-bit) revolutionary pinout commercial and industrial temperatur e ranges 3 3514 drw 03 480 ? 255 ? 30pf data out 5v . *including jig and scope capacitance. figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow, and t whz ) figure 1. ac test load ac test conditions dc electrical characteristics (1) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc ? 0.2v) 3514 drw 04 480 ? 255 ? 5pf* data out 5v . dc electrical characteristics (v cc = 5.0v 10%, commercial and industrial temperature ranges) symbol parameter test conditions min. max. unit |i li | input leakage current v cc = max., v in = gnd to v cc ___ 5a |i lo | output leakage current v cc = max., cs = v ih , v out = gnd to v cc ___ 5a v ol output low voltage i ol = 8ma, v cc = min. ___ 0.4 v v oh output high voltage i oh = ?4ma, v cc = min. 2.4 ___ v 3514 tbl 06 notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc (all address inputs are cycling at f max ) ; f = 0 means no address input lines are changing. 71124s12 71124s15 71124s20 symbol parameter com'l. com'l. ind. com'l. ind. unit i cc dynamic operating current cs < v il , outputs open, v cc = max., f = f max (2) 160 155 155 140 140 ma i sb standby power supply current (ttl level) cs > v ih , outputs open, v cc = max., f = f max (2) 40 40 40 40 40 ma i sb1 full standby power supply current (cmos level) cs > v hc , outputs open, v cc = max., f = 0 (2) v in < v lc or v in > v hc 10 10 10 10 10 ma 3514 tbl 07 input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 3ns 1.5v 1.5v see figure 1 and 2 3514 tbl 08 ac test loads
6.42 4 IDT71124 cmos static ram 1 meg (128k x 8-bit) revolutionary pinout commercial and industrial temperatur e ranges ac electrical characteristics (v cc = 5.0v 10%, commercial and industrial temperature ranges) 71124s12 (2) 71124s15 71124s20 symbol parameter min.max.min.max.min.max.unit read cycle t rc read cycle time 12 ____ 15 ____ 20 ____ ns t aa address access time ____ 12 ____ 15 ____ 20 ns t acs chip select access time ____ 12 ____ 15 ____ 20 ns t clz (1) chip select to output in low-z 3 ____ 3 ____ 3 ____ ns t chz (1) chip deselect to output in high-z 060708ns t oe output enable to output valid ____ 6 ____ 7 ____ 8ns t olz (1) output enable to output in low-z 0 ____ 0 ____ 0 ____ ns t ohz (1) output disable to output in high-z 050507ns t oh output hold from address change 4 ____ 4 ____ 4 ____ ns t pu (1) chip select to power-up time 0 ____ 0 ____ 0 ____ ns t pd (1) chip deselect to power-down time ____ 12 ____ 15 ____ 20 ns wri te cycle t wc write cycle time 12 ____ 15 ____ 20 ____ ns t aw address valid to end of write 8 ____ 12 ____ 15 ____ ns t cw chip select to end of write 8 ____ 12 ____ 15 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width 8 ____ 12 ____ 15 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 6 ____ 8 ____ 9 ____ ns t dh data hold time 0 ____ 0 ____ 0 ____ ns t ow (1) output active from end-of-write 3 ____ 3 ____ 4 ____ ns t whz (1) write enable to output in high-z 050508ns 3514 tbl 09 note: 1. this parameter guaranteed with the ac load (figure 2) by device characterization, but is not production tested. 2. there is no industrial temperature offering for the 12ns speed grade.
6.42 idt 71124 cmos static ram 1 meg (128k x 8-bit) revolutionary pinout commercial and industrial temperatur e ranges 5 notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. address must be valid prior to or coincident with the later of cs transition low; otherwise t aa is the limiting parameter. 4. oe is low. 5. transition is measured 200mv from steady state. timing waveform of read cycle no. 1 (1) timing waveform of read cycle no. 2 (1,2,4) address 3514 drw 05 oe cs data out (5) (5) (5) (5) data out valid high impedance t aa t rc t oe t acs t olz t chz t clz (3) t ohz v cc supply current t pu t pd i cc i sb . data out address 3514 drw 06 t rc t aa t oh t oh data out valid previous data out valid .
6.42 6 IDT71124 cmos static ram 1 meg (128k x 8-bit) revolutionary pinout commercial and industrial temperatur e ranges timing waveform of write cycle no. 1 ( we controlled timing ) (1,2,4) timing waveform of write cycle no. 2 ( cs controlled timing) (1,4) notes: 1. a write occurs during the overlap of a low cs and a low we . 2. oe is continuously high. during a we controlled write cycle with oe low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low transition occurs simultaneously with or after the we low transition, the outputs remain in a high impedance state. cs must be active during the t cw write period. 5. transition is measured 200mv from steady state. address cs we data out data in 3514 drw 07 (5) (2) (5) (5) data in valid high impedance t wc t aw t as t whz t wp t chz t ow t dw t dh t wr (3) (3) . cs address data in 3514 drw 08 t aw t wc t cw t as t wr t dw t dh data in valid we .
6.42 idt 71124 cmos static ram 1 meg (128k x 8-bit) revolutionary pinout commercial and industrial temperatur e ranges 7 s power xx speed x package x process/ temperature range blank i commercial (0 c to +70 c) industrial (?40 c to +85 c) y 400-mil soj (so32-3) 12 15 20 device type speed in nanoseconds 3514 drw 09 71124 x x g green blank 8 tube or tray tape and reel * ordering information * no industrial temp on 12ns speed
6.42 8 IDT71124 cmos static ram 1 meg (128k x 8-bit) revolutionary pinout commercial and industrial temperatur e ranges datasheet document history 08/05/99: updated to new format pg. 3 removed military entries on dc table pg. 4 removed note 1 and renumbered footnotes pg. 6 revised footnotes on write cycle no. 1 diagram 08/13/99: pg. 8 added datasheet document history 09/30/99: pg. 1, 3, 4, 7 added 12ns, 15ns, and 20ns industrial temperature speed grade offerings 02/18/00: pg. 3 revise i sb for industrial temperature offerings to meet commerical specifications 03/14/00: pg. 3 revised i sb to accomidate speed functionality 04/01/00: pg.4 tightened taw, tcw, twp and tdw within the ac electrical characteristics 08/09/00: not recommended for new designs 02/01/01: removed "not recommended for new designs" 10/23/08: pg.7 removed "idt" from the orderable part number 04/02/13: pg.1 removed 12ns speed from the industrial temp offering. removed idt in reference to fabrication pg.3 removed the industrial 12ns speed grade information from the dc electrical chars table 07 pg.4 added footnote 2 to ac electrical chars table 09 to indicate that there is no industrial 12ns speed pg.7 added tape & reel and green designators to the ordering information. added a footnote to the ordering information to indicate that there is no industrial 12ns speed offering the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or ipchelp@idt.com san jose, ca 95138 408-284-8200 800-345-7015 fax: 408-284-2775 www.idt.com
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